Referring to FIG. 1, which is a circuit view of a part of a conventional shift register. As shown, the gate terminal of the N-type transistor 100 receives the output signal SN−1 outputted from the previous-stage shift register and the start signal ST is transmitted to the node A1 through the turned-on N-type transistor 100. However, because both of the output signal SN−1 and the start signal ST have voltage levels roughly equal to the high operating voltage level VGH, the voltage level of the node A1 may be smaller than the original voltage level of the start signal ST after the start signal ST is transmitted to the node A1 through the N-type transistor 100; wherein the voltage level of the node A1 is obtained by subtracting the threshold voltage Vth of the N-type transistor 100 from the high operating voltage level VGH.
Because the node A1 has a voltage level value about VGH-Vth and the gate terminal of the N-type transistor 110 is fixed to the high operating voltage level VGH, the node A2 has a voltage level value about VGH-Vth as same as the node A1 has. Thus, when the voltage level of the clock signal CLK is transmitted, through the turned-on N-type transistor 120, to an output node for generating the output signal SN, the voltage level of the output signal SN may be restricted due to that the voltage level of the node A2 is smaller than the high operating voltage level VGH; and consequentially, the driving ability of the output signal SN is affected.
In addition, another issue may occur when a flat panel display uses the shift register of FIG. 1 to drive gate lines. Please referring to FIGS. 2A and 2B; wherein FIG. 2A is a circuit block view of a conventional flat panel display and FIG. 2B is a timing chart of the related signals used for driving the conventional flat panel display of FIG. 2A. As shown in FIG. 2A, the shift registers SR(1), SR(2), SR(3) and SR(4) are sequentially and alternatively arranged on two sides of the flat panel display and each is configured to drive a respective gate line. In addition, as shown in FIG. 2B, the output signal S1, S2, S3 and S4 of the shift registers SR(1), SR(2), SR(3) and SR(4) are pulled up at time points t1, t2, t3 and t4 and pulled down at time points t2, t3, t4 and t5, respectively. In addition, the clock signal XCLK is provided to the shift registers SR(1) and SR(3); and the clock signal CLK is provided to the shift registers SR(2) and SR(4).
Herein the shift register SR(3) is took as an example. When the start signal ST is transmitted to the shift register SR(3) at the time point t1, the voltage level of the node A2 in the shift register SR(3) is also pulled up to VGH-Vth. Then, with the clock signal XCLK being pulled up, the voltage level of the node A2 in the shift register SR(3) is further pulled up to about VGH-VGL (VGL is a low operating voltage level) at the time point t3. However, because the circuit design flaw of the shift register SR(3), the node A2 is in a floating state between the time points t2˜t3 and the time points t4˜t5. With the node A2 being in a floating state, the voltage level of the node A2 may drop because of the leakage current. Once the voltage level dropping process is relatively long and the voltage level of the node A2 is relatively low, the shift register SR(3) may not work normally.